The present invention relates to a video decoding apparatus of decoding encoded image data, and more particularly, to a video decoding apparatus of enhancing resistance to an error occurring in a bit stream.
In conventional video decoding apparatuses, when an error is detected during a decoding process of encoded video data, returning (resynchronization) to normal decoding is performed with respect to a group of a plurality of macroblock units. An absolute position on a picture of the leading macroblock of the group can be calculated based on the leading macroblock, by detecting a start code (marker) indicating the head of a group in a bit stream (encoded data). And the decoding process of data following the head can be resumed from a correct position on the picture.
Further, when an error is detected, data is skipped until the next sequence or the next I-picture, or a hierarchical layer higher than or equal to a GOP (Group of Picture). In the case of a B-picture, data is skipped until the next picture. In place of image data within the skipped range, an immediately previous image or a black screen is displayed (see, for example, Japanese Patent Unexamined Publication No. H09-271025).
Next, a data structure of encoded data will be described. The encoded data is composed of a leading marker, a header information portion required for decoding, and one or more pieces of encoded image data each having a constant length and containing a resynchronization marker and a plurality of variable-length codes. For example, as illustrated in FIG. 1, the data structure is composed of a leading marker 21, a header information portion 22, and a plurality of pieces of variable-length encoded data 23 in sequence. Each variable-length encoded data 23 contains a resynchronization marker 24 and a plurality of pieces of encoded data 25.
Here, MPEG4 will be described as an exemplary data encoding scheme. FIG. 2 illustrates the data structure of standard image data. In the case of the MPEG4 scheme, encoded data is constructed by a three-level structure including a VOS 31 (Visual Object Sequence), a VOL 32 (Video Object Layer), and a VOP 33 (Video Object Plane). The VOP 33 contains a VOPHeader 34 as a start code at a head thereof, followed by one or more sets of an RSM 35 (Resync Marker), a VPHeader 36 (Video Packet Header), and an MB 37 (Macroblock) as encoded image data, each set has a constant length.
The VOS 31 and the VOL 32 have various parameters related to decoding. The VOP 33 contains: a parameter related to decoding of the VOP 33, the parameter following the VOPHeader 34; an RSM 35 provided every constant length; a VPHeader 36 having various parameters related to decoding of data until the next RSM 35, a VPHeader 36 following the RSM 35; and a plurality of MBs 37 following the VPHeader 36. Each MB 37 contains an MBHeader 38 and a plurality of variable-length encoded Blocks 39. The Block 39 is variable-length encoded image data.
Next, as an exemplary decoding scheme, a Block decoding scheme called “Inter” will be described. FIG. 3 illustrates an exemplary data structure of a Block. It is assumed that image data is processed on a Block-by-Block basis. A Block contains one encoded DC value and 63 encoded AC values.
FIG. 4 is a flowchart illustrating a process of decoding a Block. As illustrated in FIG. 4, in step S401, one code is decoded. By the decoding process, the number of pieces of zero data (RUN), nonzero data (LEVEL) following the RUN, and a code (LAST) indicating that there is no nonzero data after the LEVEL, are obtained.
Next, in step S402, it is determined whether or not the value of the RUN is “0”. When the result of the determination in step S402 is “NO”, the process goes to step S403. In step S403, zero data is output. Thereafter, the process goes to step S404, in which the current value of the RUN is reduced by 1, and returns to step S402. By repeatedly performing such a procedure, zero data is eventually output a number of times corresponding to the value of the RUN.
When the result of the determination in step S402 is “YES”, the process goes to step S405. In step S405, the LEVEL (nonzero data) is output.
Next, in step S406, it is determined whether or not the value of the LAST is “1”. Here, it is defined in the specification that, in one Block, the sum of the number of pieces of zero data and the number of pieces of nonzero data is invariably 64. Therefore, when 64-th data is nonzero data, or when there is no nonzero data among data from nonzero data to 64-th data, the value of the LAST is assumed to be “1”.
When the result of the determination in step S406 is “NO” (the value of the LAST is “0”), the process goes to step S401, in which the next code is decoded. When the result of the determination in step S406 is “YES”, the process goes to step S407.
In step S407, it is determined whether or not the number of pieces of output data is 64. When the result of the determination in step S407 is “NO”, the process goes to step S408. In step S408, zero data is output, and thereafter, the process returns to step S407. By repeatedly performing such a procedure, zero data is eventually output a number of times corresponding to the value of the RUN.
When the result of the determination in step S407 is “YES”, the Block decoding process is ended.